www.rfm.com e-mail: info@rfm.com page 1 of 4 ?2008 by rf monolithics, inc. DR5001 - 4/8/08 electrical characteristics, 2.4 kbps on-off keyed characteristic sym notes minimum typical maximu units operating frequency fo 868.15 868.55 mhz modulation type ook data rate 2.4 19.2 kbps receiver performance (ook @ 2.4 kbps) input current, 3 vdc supply i r 1.8 ma input signal for 10 -4 ber, 25 c -100 dbm rejection, 30 mhz r rej 55 db sleep to receive switch time(100 ms sleep, -85 dbm signal) tsr 3 200 s sleep mode current is 5 a power supply voltage range vcc 2.7 3.5 vdc operating ambient temperature t a -20 +65 c ? designed for short-range wireless data communications ? supports up to 19.2 kbps encoded data transmissions ? 3 v, low current operation plus sleep mode ? ready to use oem module the DR5001 receiver module is ideal for short-ran ge wireless data applications where robust operation, small size and low power consumption are requi red. the DR5001 utilizes rfm?s rx6001 amplifier- sequenced hybrid (ash) architecture to achieve this unique blend of charac teristics. the receiver rx6001 is sensitive and stable. a wide dynamic range log detector provides robust performance in the presence of on- channel interference or noise. two stages of saw filter ing provide excellent receiver out-of -band rejection. the DR5001 includes the rx6001 plus all configurati on components in a ready-to-use pcb assembly excellent for prototyping and intermediate volume production runs. absolute maximum ratings rating value units power supply and all input/output pins -0.3 to +4.0 v non-operating case temperature -50 to +100 c soldering temperature (10 seconds) 230 c 868.35 mhz receiver module DR5001 .70 .25 .20 .165 .70 .10 dr5000 outline drawing dimensions in inches DR5001 outline drawing dr5000 pin out rf gnd rfio agc/vcc pk det nc rx bbo rx data ctr0 ctr1 gnd vcc lpf adj 1 2 3 4 58 9 10 11 12 13 14 67 gnd gnd DR5001 pin out
www.rfm.com e-mail: info@rfm.com page 2 of 4 ?2008 by rf monolithics, inc. DR5001 - 4/8/08 pin desciptions pin name description 1 agc/vcc this pin is connected directly to the receiver agccap pin. to disable agc operation, this pin is tied to vcc. to enable agc operation, a capacitor is placed between this pin and ground. th is pin controls the agc reset operation. a capacitor between this pin and ground sets the minimum time the agc will hold-in onc e it is engaged. the hold-in time is set to avoid agc chat- tering. for a given hold-in time t agh , the capacitor value c agc is: c agc = 19.1* t agh , where t agh is in s and c agc is in pf a 10% ceramic capacitor should be used at this pin. the value of c agc given above provides a hold-in time between t agh and 2.65* t agh , depending on operating voltage, temperature, etc. the hold-in time is chosen to allow the agc to ride through the longest run of zero bits that can occur in a received data st ream. the agc hold-in time can be greater than the peak detector decay time, as discussed below. however, the agc hold-in time should not be set too long, or the receiver will be slow in returning to full sensitivity once the agc is engaged by noise or interference. t he use of agc is optional when using ook modulation with data pulses of at least 30 s. active or latche d agc operation is required for ask modulation and/or for data pulses of less than 30 s. the agc can be latched on onc e engaged by connecting a 150 k resistor between this pin and ground, instead of a capacitor. agc operation depends on a functioning peak detector, as discussed below. the agc capacitor is discharged in the receiver power-down (sleep) mode. note that provisions are made on the ci rcuit board to install a jumper between this pin and the junction of c2 and l3. installing the jumper allows either this pin or pin 9 to be used for the vcc sup ply when agc operation is not required. 2 pk det this pin is connected directly to the receiver pkdet pin. this pin controls the peak detector operation. a capacitor between this pin and ground sets the peak detector attack and decay times, which have a fixed 1:1000 ratio. for most applications, the attack time constant should be set to 6.4 ms with a 0.027 f capacitor to ground. (this matches the peak detector decay time constant to the time constant of the 0.1 f coupling capacitor c3.) a 10% ceramic capacitor should be used at this pin. the peak detector is used to drive the "db-below-peak" data slic er and the agc release function. the agc hold-in time can be extended beyond the peak detector decay time with the agc capa citor, as discussed above. where low data rates and ook modulation are used, the "db-below-peak" data slicer and the ag c are optional. in this case, the pkdet pin can be left uncon- nected, and the agc pin can be connected to vcc to reduce the number of external components needed. the peak detector capacitor is discharged in the receiver power-down (sleep) mode. see the description of pin 3 below for further information. 3 rx bbo this pin is connected directly to the receiver bbout pin. on the circuit board, bbout also drives the receiver cmpin pin through c3, a 0.1 f coupling capacitor (t bbc = 6.4 ms). rx bbo can also be used to drive an external data recovery process (dsp, etc.). the nominal output impedance of this pin is 1 k. the rx bbo signal changes about 10 mv/db, with a peak-to- peak signal level of up to 675 mv. the signal at rx bbo is riding on a 1.1 vdc value that varies somewhat with supply voltage and temperature, so it should be coupled through a capacitor to an external load. a load impedance of 50 k to 500 k in parallel with no more than 10 pf is recommended. note the agc reset function is driven by the signal applied to cmpin through c3. when the receiver is in power-down (sl eep) the output impedance of this pin becom es very high, preserving the charge on the coupling capacitor(s). the value of c3 on the circuit board has been chosen to match typical data encoding schemes at 2.4 kbps. if c3 is modified to support higher data rates and/or di fferent data encoding schemes and pk det is being used, make the value of the peak detector capacitor about 1/3 the value of c3. 4 rx data rx data is connected directly to the rece iver data output pin, rxdata. this pin will drive a 10 pf, 500 k parallel load. the peak current available from this pin increases with the receiv er low-pass filter cutoff frequency. in the power-down (sleep) or receive mode, this pin becomes high impedanc e. if required, a 1000 k pull-up or pull- down resistor can be used to establish a definite logic state when this pin is high impedance (do not c onnect the pull-up resistor to a supply voltage higher than 3.5 v dc or the receiver will be damaged). th is pin must be buffered to succ essfully drive low-impedance loads. 5 nc 6, 7 gnd 8lpf adj this pin is the receiver low-pa ss filter bandwidth adjust, and is connected directly to the receiver lpfadj pin. r6 on the circ uit board (330 k) is connected between lpfadj and ground will be in pa rallel with any external resistor connected to lpf adj. the filter bandwidth is set by the parallel resistance of r6 and the external resistor (if used). the equivalent resistor value can range from 330 k to 820 ohms, providing a filter 3 db bandwidth f lpf from 4.4 khz to 1.8 mhz. the 3 db filter bandwidth is determined by: f lpf = 1445/ (330*r lpf /(330 + r lpf )), where r lpf is in kilohms, and f lpf is in khz a 5% resistor should be used to set the filter bandwidth . this will provide a 3 db filter bandwidth between f lpf and 1.3* f lpf with variations in supply voltage, temperature, etc. the filt er provides a three-pole, 0.05 degree equiripple phase response. t he peak drive current available from rxdata increases in proportion to the filter bandwidth setting. as shipped, the receiver mod- ule is set up for nominal 2.4 kbps operation. an external resistor can be added between pin 8 and ground to support higher data rates. preamble training times will not be decreased, however, unless c3 is replaced with a smaller capacitor value (see the descriptions of pins 2 and 3 above). refer to sections 1. 4.3, 2.5.1 and 2.6.1 in the ash transceiver designer's guide for additional information on data rate adjustments.
www.rfm.com e-mail: info@rfm.com page 3 of 4 ?2008 by rf monolithics, inc. DR5001 - 4/8/08 data out 3 vdc 2.4 kbps application circuit 12345 8 9 10 11 12 13 14 dr3000 7 6 DR5001 data out 3 vdc 19.2 kbps application circuit 12345 8 9 10 11 12 13 14 7 6 33 k DR5001 pin name description 9vcc this is the positive supply voltage pin for the module. the operati ng voltage range is 2.7 to 3.5 vdc. it is also possible to u se pin 1 as the vcc input. please refer to the pin 1 description above. 10 gnd this is the supply voltage return pin. 11 ctr1 ctr1 is connected to the cntrl1 control pin on the receiver. ctr1 and ctr0 select the transceiver operating modes. ctr1 and ctr0 both high place the unit in the receive mode. ctr1 and ctr0 both low place the unit in the power-down (sleep) mode. ctr1 is a high-impedance input (cmos compatible). this pin must be held at a logic level; it cannot be left uncon- nected. at turn on, the voltage on this pin and ctr0 should ri se with vcc until vcc reaches 2. 7 vdc (receive mode). thereaf- ter, any mode can be selected. 12 ctr0 ctr0 is connected to the cntrl0 control pi n on the receiver ctr0 is used with ctr1 to control the operating modes of the receiver. ctr0 is a high-impedance input (cmos compatible). this pin must be held at a logic level; it cannot be left uncon- nected. at turn on, the voltage on this pin and ctr1 should ri se with vcc until vcc reaches 2. 7 vdc (receive mode). thereaf- ter, any mode can be selected. 13 rfio rfio is the rf input/output pin. a matching circuit for a 50 ohm load (antenna) is implem ented on the circuit board between this pin and the receiver saw filter transducer. 14 rf gnd this pin is the rf ground (return) to be used in conjunction with the rfio pin. fo r example, when connecting the transceiver module to an external antenna, the coaxial cable ground is connected this pin and the coaxial cable center conductor is con- nected to rfio.
www.rfm.com e-mail: info@rfm.com page 4 of 4 ?2008 by rf monolithics, inc. DR5001 - 4/8/08 note: preliminary specifications, subject to change without notice. r3 r4 r8 r1 r2 r6 c3 c2 l2 c1 l1 c4 c5 + ash receiver 20 1 11 10 ctr0 (12) ctr1 (11) vcc (9) lpf adj (8) gnd (6, 7, 10) rfio (13) rf gnd (14) agc/vcc (1) pk det (2) rx bbo (3) rx data (4) DR5001 schematic
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